1. Field of the Invention
The present invention relates to a semiconductor memory device having spare memory cells for repairing defects in normal memory cells and, more particularly, to checking spare memory cells for defects.
2. Description of the Background Art
FIG. 30 is a plan view of principal portions of a conventional dynamic semiconductor memory device (referred to hereinafter as a DRAM). In FIG. 30, the reference numeral 141 designates an area wherein a column of sense amplifiers are arranged (a sense amplifier forming area); 142 designates an area wherein a group of memory elements are arranged (memory cell array); 143 designates a row decoder for activating a word line specified by a row address signal for selecting a cell in the memory cell array 142; and 144 designates a column decoder for activating a bit line specified by a column address signal for selecting a cell in the memory cell array 142.
FIG. 31 conceptually illustrates the structure of an area 145 shown in FIG. 30. In FIG. 31, the reference numeral 146 designates memory cells for constituting the memory cell array 142; the reference character 147a designates word lines provided in respective rows of the normal memory cells and controlled by a normal row decoder 143a so that they are active/inactive; 147b designates a word line provided in a spare cell row in which spare memory cells are arranged and controlled by a spare row decoder 143a so that it is active/inactive; 148a designates bit lines provided in respective normal columns in which the normal memory cells are arranged and controlled by a normal column decoder 144a of the column decoder 144 so that they are active/inactive; and 148b designates bit lines provided in respective spare memory cell columns in which the spare memory cells are arranged and controlled by a spare column decoder 144b of the column decoder 144 so that they are active/inactive.
The DRAM shown in FIG. 31 has a redundant construction for repairing a defect. Each memory cell array 142 includes one or more spare rows and one or more spare columns. If a memory cell is defective, the row or column containing the defect is electrically replaced with a spare row or spare column by the laser fuse programming or the like to repair the defect.
FIG. 32 is a plan view of a conventional dynamic semiconductor memory device. In FIG. 32, the reference numeral 200 designates a storage area of the dynamic semiconductor memory device; 201 designates an area wherein a column of sense amplifiers are arranged (a sense amplifier forming area); 202 designates an area wherein a group of memory elements formed between the areas 201 wherein a plurality of columns of sense amplifiers are arranged respectively are arranged; 203 designates word line backing areas for connecting metal interconnecting lines having a relatively low resistance; and 204 designates areas wherein interconnecting lines having a relatively high resistance are formed in a layer different from the word line backing areas 203 and intersecting the sense amplifier forming areas 201.
FIG. 33 conceptually illustrates the structure of the word line backing areas 203 shown in FIG. 32. In FIG. 33, the reference numeral 205 designates aluminum interconnecting lines having a relatively low resistance; and 206 designates polycide interconnecting lines having a relatively high resistance and connected in parallel with the aluminum interconnecting lines 205.
FIG. 34 is a block diagram of a memory cell block of the dynamic semiconductor memory device. In FIG. 34, the reference characters 141a and 141c designate sense amplifier forming areas wherein sense amplifiers for reading data from the normal memory cells are formed; 141b and 141d designate sense amplifier forming areas wherein sense amplifiers for reading data from the spare memory cells are formed; 148c designates bit line pairs for transmitting data read from the normal memory cells; and 148d designates bit line pairs for transmitting data read from the spare memory cells. Like reference numerals and characters are used to designate elements corresponding to those of FIG. 31.
The conventional semiconductor memory device constructed as above described has failed to effectively repair defects in the memory cells arranged in the spare rows and spare columns.